Interference Suppression in Bit-Serial Data Streams

ABSTRACT

Described is an apparatus for suppressing spurious spectral lines in a frame based bit-serial data stream, in which frames include payload data and frame markers. The apparatus includes means ( 16 ) for randomizing first frame marker elements (START) in a first position within each frame and means ( 18 ) for correlating second frame marker elements (STOP) in a second position within each frame with the randomized first frame marker element.

TECHNICAL FIELD

The present invention relates to suppression of interference, andparticularly to suppression of spurious spectral lines in frame basedbit-serial data streams.

BACKGROUND

In, for example, digital radio designs there are a large number ofsignal paths containing high-speed, high-resolution digital data.Typical examples are: (a) from an ADC (Analog-to-Digital Converter) to asubsequent DSP (Digital Signal Processor); (b) from a DSP to a DAC(Digital-to-Analog Converter) used in a radio transmitter; (c) betweenDSPs within a radio base station; (d) between sub-systems within a radiobase station, e.g. between different boards.

It is desirable to reduce the amount of routing between ASICs(Application Specific Integrated Circuits), FPGAs (Field-ProgrammableGate Arrays), ADCs and DACs. In order to do that, DSPs anddata-converter parts are migrating towards the use of bit-serial, ratherthan bit-parallel digital interfaces. Some benefits are:

The digital interface between ADCs/DACs and ASICs results in asubstantially reduced number of bus wires, thus reducing the board spaceoccupied by signal routing.

Dramatically reduced number of output/input pins per component allowsfor integration of more functionality in a single package, thus furtherreducing board space. An example is dual/quad/octal ADCs/DACs. It alsotheoretically enables a larger number of digital signal paths to behandled by a single ASIC before becoming constrained by the pin-count.

A bit-serial interface may use any available electrical standards, suchas LVDS (Low-Voltage Differential Signaling) and CML (Current-ModeLogic), or a custom technology. Available coding standards, such as 8b/10 b-coding may or may not be used, and the clock may or may not beembedded in the data bit-stream (for very high bit-rates, e.g. over 1Gb/s, an embedded clock/sync is usually preferred over an extra clockline in parallel with the data).

A bit-serial channel with embedded clock/sync has the disadvantage thatframe marker bits or bit patterns have to be inserted into thetransmission to mark the start and/or stop of a transmission frame. Therepetitive nature of such start/stop markers generates spurious spectrallines at k*f_(b)/n, where f_(b) is the bit-rate of the bit-serialchannel, n is the transmission frame length in bits, and k is aninteger. The end result is that these spurious spectral lines may leadto undesirable interference.

SUMMARY

An object of the present invention is to suppress spurious spectrallines in bit-serial data streams with frame markers.

This object is achieved in accordance with the attached claims.

Briefly, the present invention is based on the idea of randomizing apart of the frame markers to remove the repetitive marker patterns andto correlate another part to the randomized part. In this way thespurious spectral lines originating from these patterns are convertedinto wide-band noise. The result is that no particular frequencycomponent dominates the spectrum, which reduces the interference. Due tothe correlation between the parts of each frame marker the received datastream may easily be synchronized at the receiving end without anyknowledge of the randomization algorithm used at the transmitting end.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with further objects and advantages thereof, maybest be understood by making reference to the following descriptiontaken together with the accompanying drawings, in which:

FIG. 1 is an example of an application involving a bit-serial interface;FIG. 2 is another example of an application involving a bit-serialinterface;

FIG. 3 is another example of an application involving a bit-serialinterface;

FIG. 4 is another example of an application involving a bit-serialinterface;

FIG. 5 illustrates the format of a typical bit-serial data stream;

FIG. 6 is a block diagram illustrating the principles of a conventionalbit-serial interface;

FIG. 7 illustrates the essential features of the spectrum of a typicalbit-serial data stream generated by the interface in FIG. 6;

FIG. 8 is a block diagram of a first embodiment of the transmitting endof a bit-serial interface in accordance with the present invention;

FIG. 9 illustrates a first embodiment of a bit-serial data streamprovided with randomized markers in accordance with the presentinvention;

FIG. 10 illustrates a second embodiment of a bit-serial data streamprovided with randomized markers in accordance with the presentinvention;

FIG. 11 illustrates the principles of frame synchronization of a bitserial data stream provided with randomized frame markers in accordancewith the present invention;

FIG. 12 is a first embodiment of an apparatus for synchronizing abit-serial data stream provided with randomized frame markers inaccordance with the present invention;

FIG. 13 is a second embodiment of an apparatus for synchronizing abit-serial data stream provided with randomized frame markers inaccordance with the present invention;

FIG. 14 is a block diagram of a another embodiment of the transmittingend of a bit-serial interface in accordance with the present invention;

FIG. 15 is a flow chart illustrating an embodiment of the suppressionmethod in accordance with the present invention; and

FIG. 16 is a flow chart of an embodiment of the synchronization methodin accordance with the present invention.

DETAILED DESCRIPTION

Before the invention is described in detail, a few applications ofbit-serial interfaces will be described with reference to FIG. 1-4.

FIG. 1 is an example of an application of a bit-serial interface. Inthis case analog RF (Radio Frequency) signal is received by an RF-stage,where it is digitized by an ADC (either directly at RF or afterdown-conversion to intermediate frequency or baseband). Conventionallythe ADC has been connected to a DSP over a bit-parallel interfacerepresented by the solid arrow. The reason is that the ADC delivers thebits of digital samples in parallel. However, as noted above, thepresent trend is to replace the bit-parallel interface with a bit-serialinterface.

FIG. 2 is another example of an application of a bit-serial interface.This is essentially the reverse of FIG. 1. As in the example of FIG. 1the conventionally used bit-parallel interface between the DSP and DACmay be replaced by a bit-serial interface.

FIG. 3 is an example involving a bit-parallel interface between twoDSPs, which may be replaced by a bit-serial interface.

FIG. 4 is an example involving a bit-parallel interface between twosubsystems, for example two printed circuit boards, which may bereplaced by a bit-serial interface.

The basic principles of a bit serial interface will now be describedwith reference to FIG. 5 and 6.

FIG. 5 illustrates the format of a typical bit-serial data stream. Theactual useful data, typically called payload, is divided into N-bitsequences framed by a marker or marker pattern [A, Ω]. As an example,the N-bit payload may include 8 data bits (in another embodiment thepayload may include 7 data bits and a parity bit) surrounded by a firstmarker element forming a start bit A and a second marker element forminga stop bit Ω. The marker [A, Ω] is typically selected among thefollowing alternatives:

[A, Ω]=[0,0], [0,1], [1,0] or [1,1]

FIG. 6 is a simple block diagram illustrating the principles of aconventional bit-serial interface. This example illustrates an ADCconnected to a DSP over a bit-serial interface. On the transmitting sidethe bit-serial interface includes a parallel-to-serial converter 10.Each digitized 8-bit sample is framed by a start bit A=1 and a stop bitΩ=0 and then the resulting 10 bits are converted into bit-serial form byconverter 10.

On the receiving side of the bit-serial interface, a synchronizer 12detects the repeated and known [1,0] marker formed by the start/stopbits. After synchronization the payload bits are forwarded to aserial-to-parallel converter 14, which outputs the original digitizedsamples in parallel form to the DSP for digital signal processing.

The detection of the synchronization or marker pattern is simple due tothe fact that the marker pattern is repetitive and known on thereceiving side of the interface. However, this simplicity has its price,as illustrated in FIG. 7, which shows the general features of thespectrum of a bit-serial data stream comprising 8-b random payload datausing a 10-b frame with markers [A, Ω]=[1,0]. As shown, the repetitivenature of the markers generates spurious spectral lines at k*f_(b)/10above the “noise level” produced by the random payload.

By using randomized frame markers in accordance with the presentinvention, the repetitive nature of the start/stop bits is scrambled andthus the spurious spectral lines seen in FIG. 7 will be transformed intowide-band noise, effectively removing these spurious spectral lines. Theresult will be a spectrum without pronounced interfering peaks at thecost of a slightly raised noise floor.

In accordance with an embodiment of the present invention the markers[A, Ω] may be selected among the following alternatives:

[A, Ω]=[r_(i), r_(i)], [r_(i), r _(i)], [r _(i), r_(i)]or [r _(i), r_(i)]

where r_(i) is taken from a random bit-sequence, and r _(i) is theinverse of r_(i). The random bit sequence can be generated with apseudo-random binary number generator or a “true” random binary numbergenerator (e.g. bits generated by digitizing a thermal noise voltage ora noisy signal) if the requirements on randomness are exceptionallyhigh. Random number generation is well understood, and comprehensivelytreated in the literature, e.g. in [1,2], and is therefore not describedhere.

FIG. 8 is a block diagram of a first embodiment of the transmitting endof a bit-serial interface in accordance with the present invention. Arandom signal generator 16 generates a pseudo random or genuinely randombit sequence. This bit sequence is forwarded to parallel/serialconverter 10 to form a pseudo random or truly random start bit sequence.The bit sequence from random 30 signal generator 16 is also forwarded toa co-coordinating or correlating unit 18. The bit sequence from unit 18is forwarded to parallel/serial converter 10 to form a stop bitsequence. The purpose of unit 18 is to co-ordinate each stop bit withthe start bit in each marker. In one embodiment this may be done byinverting the value of each start bit. In a simpler embodiment the stopbits may be equal to the start bits, in which case unit 18 can beomitted, so that the stop bit simply will be a copy of the start bit.Furthermore, the roles of the start/stop bits may be reversed, i.e. thestop bit sequence may be (pseudo) random and control the start bitsequence.

The exact pattern of start/stop (or sync) bits can be implemented withsome variation without deviating from the underlying principle of thepresent invention. Two possible implementations are indicated in FIG. 9and 10. FIG. 9 shows a start/stop format where the payload data isenclosed by the two correlated marker bits. FIG. 10 shows a“frame-divider” format where the payload data words are separated by twoadjacent correlated marker bits.

FIG. 11 illustrates the principles of frame synchronization of a bitserial data stream provided with randomized frame markers in accordancewith the present invention. In this embodiment the data stream isassumed to have the format illustrated in FIG. 9, i.e. the randomizedstart and stop bits are equal and enclose each frame. As illustrated inFIG. 11, the data stream slides through a detection window, which picksup two bits separated by the expected bit distance between the start andstop bits in a frame. These bits are forwarded to an inverting XOR gate,which outputs “1” if the bits are equal a “0” if they are not equal.Thus, the actual bit values are not essential. The essential feature isthat they are equal (in this embodiment) at the synchronizationposition, such as the window position in FIG. 11( a). In this way theoutput is “1” with certainty when the window is in a synchronizationposition. In FIG. 11( b) the window has been shifted 1 bit position. Inthis case the output of the inverted XOR gate will be either “1” or “0”,since data bit 1 of the payload and marker element r_(i+1) have now beenpicked up by the window. Since there is no correlation between thesebits, there is a 50% probability for each outcome. The same commentstypically apply to the situation in FIG. 11( c), in which two data bitsare compared (assuming that the payload bits are essentiallyuncorrelated). In FIG. 11( d) the next start/stop pair is encountered,which results in a “1” output from the inverted XOR gate with certainty.

It is appreciated that occasionally the window will give a “1” outputalso in “non-marker” positions (typically with a rate of 50%), but thatthe marker positions will always give a “1” output. Thus, by monitoringthe output of the window over several frames, the synchronizing positioncan be found by requiring that all windows that are separated by aninteger number of frames must give a “1” output. FIG. 12 is anembodiment of an apparatus for synchronizing a bit-serial data streambased on this idea. In FIG. 12 the bit-serial data stream to besynchronized is forwarded to a shift register with a length of severalframes, for example between 5 and 40 frames. The expected taps of startand stop bits are forwarded to corresponding inverted XOR gates, one foreach frame. The outputs of the inverted XOR gates are connected to anAND gate, the output of which delivers a synchronization signal when allinverted XOR gates output a logical “1” signal, i.e. when all monitoredbit positions of the shift register indicate that start/stop bits havebeen found. This is the situation illustrated in FIG. 12. If it can beassumed that the payload bits are essentially uncorrelated, it is veryunlikely that false synchronization positions will be found. Theprobability of this to happen decreases very rapidly with the length ofthe shift register (or the number of monitored frames, p+1).

FIG. 13 is a second embodiment of an apparatus for synchronizing abit-serial data stream provided with randomized frame markers inaccordance with the present invention. This embodiment is tailored forthe data stream format of FIG. 10. The difference with regard to theembodiment of FIG. 12 is that other shift register taps are monitored.

In the embodiments of FIG. 12 and 13 the start and stop bits were equal.However, embodiments where they are unequal (but correlated) may beobtained by simply omitting the inverters after the XOR gates.

Phase/sync-recovery in the receiver may improve if additional markerbits are inserted into the frame. This will guarantee an increasedswitching density of the bit-stream if this is desirable. Furthermore,placing additional marker bits at irregular intervals that do notrepeat, e.g. positions {1, 3, 6, 10} in a 10-b frame, may help the phaselocking of the receiver (However, it should be noted that liberal use ofadditional marker bits will waste significant transmission bandwidth.).If additional marker bits are used, these may be based on the samerandom bit r_(i) as the other two marker bits—or they may be based onanother (independent) random bit s_(i) for smoother randomization of themarkers and/or payload data. In the latter case they must be added inpairs, one randomized bit and one correlated bit. Random bits s_(i) canbe from the same random bit source as r_(i), or a second random bitsource. A second group of XOR or XNOR gates, similar to the ones shownin FIG. 12 and 13, detects the two or more s_(i) marker bits. Fullsynchronization requires all r_(i) and s_(i) detectors to output “1”.

As has been shown above, it is essential that the marker elements of arandomized marker are correlated to enable simple synchronization at thereceiver. However, if a primary marker element is randomized, thesecondary marker element(s) do not necessarily have to be equal orinverted versions of the primary element. Since the synchronization isbased on the fact that the marker elements should be correlated, it isactually only required that they have a stronger correlation than thebits of payload data. Thus, the secondary marker elements may begenerated from the primary marker elements by a function that has aslight built in randomness. This will further suppress the spuriousspectral lines. However, in such an embodiment the inverted XOR gates inFIG. 12 and 13 will not always generate hits (an “1” output) in thecorrect synchronization position, which means that the AND gate has tobe replaced by, for example, a counter that counts the number of hits.The synchronization position may then be found by selecting the positionthat gives the highest number of hits. Such a synchronization approachmay also be desirable when the bit-serial data is transmitted over anoisy channel such that all frames are unlikely to be detectedcorrectly.

In the above description it was assumed that the payload datatransmitted over the bit-serial channel was random. In a generalapplication that may not necessarily be true. There may be situationswhere a fixed-pattern or otherwise repetitive data (such as a carriersignal) is transmitted over the channel for an extended period of time.Such data has a spurious content of its own, and it will show up asspectral peaks or lines in the frequency spectrum even if the framemarkers are randomized. In an embodiment of the present invention thesespurious spectral lines may be suppressed by scrambling the payload datawith the randomized frame markers already present in the transmission.Since the random bit r_(i) used to create the frame markers originatesfrom a random bit sequence, its actual value 0 or 1 varies randomly (orpseudo-randomly) from frame to frame. Thus it can also be used toscramble the transmitted payload data. A straightforward scramblingscheme would be to XOR the payload data bits with r_(i) (or r _(i)) asillustrated in FIG. 14. An important advantage of scrambling inaccordance with the present invention is that the XOR key is alreadyembedded in the transmitted data, which is critical to high bit-ratetransmission channels. Optional parity bits may also be modified in thisway.

If the marker elements include more than one bit, a part of the payloadmay be scrambled by a first random bit sequence r_(i), and a second partmay be scrambled by a second random sequence s_(i), etc.

FIG. 15 is a flow chart illustrating an embodiment of the suppressionmethod in accordance with the present invention. Step S1 randomizes afirst frame marker element in a given position in a frame. Step S2correlates a second marker element in another position in the frame withthe randomized first marker element. Step S3 goes to the next frame, andthen the procedure is repeated.

FIG. 16 is a flow chart of an embodiment of the synchronization methodin accordance with the present invention. Step S4 detects pairs of dataelements separated by M bits, where M is the expected distance betweenfirst and second frame marker elements. Step S5 determines thecorrelation between data elements in each pair. Step S6 organizes thepairs into sets in such a way that each set includes pairs separated bya whole frame (the distance between the first data element in a pair andthe first data element in the next pair is a frame length). Step S7determines the total correlation for each set. Step S8 determines theset having the highest total correlation. This will determine thesynchronization position.

Although the present invention has been described with reference towired bit-serial interfaces, it is appreciated that the same principlesmay equally be applied to optical as well as wireless interfaces.

Furthermore, it is appreciated that the invention is not limited tosingle bit marker elements, but is also applicable to multi-bit markerelements.

The invention is also compatible with the insertion of additional databits, e.g. for

-   Padding data to a certain word length (or achieving a certain    bit-rate in the channel).-   Sending additional down-stream data, which may be used for system    calibration/control/communication.-   Additional parity/error-correction bits.

For the purpose of describing the invention these additional bits areequivalent to an increase in the content word length N, and thus alreadycovered by the previous description.

Payload data can also be coded before framing/transmission in order to:

-   Improve switching density for improved phase recovery.-   Otherwise aid phase-locking and reception on the receiver side.-   Add error detection/correction beyond that of the parity bit.-   Further control spectral content of payload data.-   Achieve DC-neutrality in transmission.

There may be situations where one wishes to transmit N-b data words overa channel that has a different, fixed, frame size. Example: The channelhas an n-b fixed frame-size including start/stop markers as previouslydescribed. The data source is an N-b ADC. Solution: Use the inventiontwice:

-   (1) Serialize the ADC source data using two frame-marker bits, and    optional parity bits, as described previously. Scramble payload data    here and/or in the next step.-   (2) Transmit the serialized & framed data (including its marker &    possible parity/dummy/control bits) by blindly splitting/combining    it into chunks fitting the payload core of the channel with    transmission frame length n.-   (3) The receiver unpacks the payload chunks from the transmission    frames and combines them into a secondary bit-stream, which is    passed to the last step.-   (4) In the last step, the secondary bit-stream is searched for frame    markers, and the N-b data is unpacked and possibly de-serialized.

Using the invention in a multi-layered fashion enables the definition ofa fixed-format channel interface (circuit block) that will handle phaselocking and the raw transmission over the channel. The actual dataformat is handled in a second layer of packing/unpacking—thus it is tosome extent separated from the operation of the channel itself.

The transmission channel of steps (2) and (3) in the previous sectionmay use a different protocol than that of the invention. As an example,an 8 b/10 b channel may be used for the physical transmission layer. Theinvention can then be used to frame, and keep track of, the datacontent, as well as scrambling it in order to improve the spectralproperties of the physical transmission.

In order to further suppress interference emissions in certain frequencybands, the random bit sequence used for randomization may be other thana white-noise sequence, i.e. a colored noise sequence. As an example, alow-pass shaped sequence would improve noise performance in the RF & IFbands, at the cost of increased noise in the baseband.

The present invention has several advantages, some of which are:

-   The invention significantly suppresses the spurious frequency    content of a synchronized bit-serial digital transmission, and thus    leads to an improved performance in interference-sensitive    systems—specifically in radio base-stations.-   Synchronization is simple and requires no knowledge of the algorithm    or process used for randomization.-   It also has a very broad, general application for interference    control in any interference-sensitive system where bit-serial    digital interfaces are used.-   Payload data scrambling can be implemented with essentially    zero-increase in complexity.-   With payload data scrambling, and a proper selection of random bit    sequence, a statistically DC-neutral transmission can be guaranteed.-   The invention is applicable to the bit-serial transmission of data    packages with arbitrary frame-lengths.

It will be understood by those skilled in the art that variousmodifications and changes may be made to the present invention withoutdeparture from the scope thereof, which is defined by the appendedclaims.

REFERENCES

-   [1] D. W. Clark, and L.-J. Weng, “Maximal and Near-Maximal Shift    Register Sequences: Efficient Event Counters and Easy Discrete    Logarithms”, IEEE Trans. Computers, pp. 560-568, Vol. 43, No. 5, May    1994, IEEE.-   [2] T. Ritter, “The Efficient Generation of Cryptographic Confusion    Sequences”, Cryptologia, pp. 81-139, Vol. 15, No. 2, Apr. 1991.

1. A method of suppressing spurious spectral lines in a frame-basedbit-serial data stream, wherein frames include payload data and framemarkers, said method including the steps of: randomizing first framemarker elements in a first position within each frame; and, correlatingsecond frame marker elements in a second position within each frame withcorresponding randomized first frame marker elements.
 2. The method ofclaim 1, further including the step of scrambling payload data in eachframe with one of said frame marker elements.
 3. The method of claim 1,wherein each frame marker element is represented by a single bit.
 4. Themethod of claim 1, further including the step of correlating at leastone further frame marker element with said first frame marker element.5. The method of claim 1, further including the step of randomizing andcorrelating at least one further frame marker element pair.
 6. Themethod of claim 1, wherein randomization is performed by a colored noisesequence.
 7. An apparatus for suppressing spurious spectral lines in aframe-based bit-serial data stream, in which wherein frames includepayload data and frame markers, said apparatus including: means forrandomizing first frame marker elements in a first position within eachframe; and, means for correlating second frame marker elements in asecond position within each frame with corresponding randomized firstframe marker elements.
 8. The apparatus of claim 7, further includingmeans for scrambling payload data in each frame with one of said framemarker elements.
 9. The apparatus of claim 6, further including meansfor randomizing and correlating further marker elements.
 10. Theapparatus of claim 7, further including means for randomizing by acolored noise sequence.
 11. A method of synchronizing a frame-basedbit-serial data stream, wherein frames include payload data and framemarkers, said method including the steps of: detecting groups ofseparated data elements. determining the correlation between the dataelements in each group; determining the total correlation of severalsets of groups of data elements in which the groups are separated bywhole frame lengths; and, synchronizing said data stream to a set havingthe highest total correlation.
 12. The method of claim 11, wherein eachgroup includes two data elements.
 13. An apparatus for synchronizing aframe-based bit-serial data stream, wherein frames include payload dataand frame markers, said apparatus including: means for detecting groupsof separated data elements; means for determining the correlationbetween the data elements in each group; means for determining the totalcorrelation of several sets of groups of data elements in which thegroups are separated by whole frame lengths; and, means forsynchronizing said data stream to a set having the highest totalcorrelation.
 14. A bit-serial data stream, wherein frames includepayload data and frame markers, said stream including: randomized firstframe marker elements in a first position within each frame; and, secondframe marker elements in a second position within each frame, whereineach second frame marker element is correlated with a correspondingrandomized first frame marker element.